@inproceedings{CAD4X-C-2010,

author = {Jaehyun Park and Donghwa Shin and Massoud Pedram and Naehyuck Chang},

title = {Accurate Modeling and Calculation of Delay and Energy Overheads of Dynamic Voltage Scaling in Modern High-Performance Microprocessors},

booktitle = {Proceedings of Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)},

year = {2010},

pages  = {419--424},

location = {Austin, USA},

month = {August},

note = {},

abstract = {Dynamic voltage and frequency scaling (DVS) has been studied for well over a decade, and even commercial systems widely support DVS nowadays. Nevertheless, existing DVS transition overhead mod- els do not accurately reflect modern DVS architectures including modern DC–DC converters, PLL (Phase Lock Loop), and voltage and frequency change policies. Incorrect DVS overhead models pre- vent one from achieving the maximum energy gain, by mislead- ing the DVS control policies. This paper introduces an accurate DVS overhead model, in terms of both energy consumption and time penalty, through detailed observation of modern DVS setups and voltage and frequency change guidelines from vendors. We intro- duce new major contributors to the DVS overhead including the per- formance underdrive loss of the DVS-enabled microprocessor, addi- tional inductor IR loss, and so on, as well as consideration of power efficiency from discontinuous-mode DC–DC conversion. Our DVS overhead model enhances the DVS overhead model accuracy from 86% to 238% for Intel Core2 Duo E6850 and LTC3733.},

keywords = {DVFS, DVS overhead model, PLL, DC–DC converter},

}